The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Integrated circuit devices, such as transistors, are formed on semiconductor dies or chips having features that continue to scale in size to smaller dimensions. The shrinking dimensions of these features are challenging conventional routing configurations of power signals and/or ground signals for semiconductor dies in an electronic package assembly (or semiconductor package). For example, the routing of power signals and/or ground signals using conventional pin technologies for multiple semiconductor dies in a same electronic package assembly may considerably increase manufacturing cost of the electronic package assembly.
FIG. 1A illustrates an example conventional semiconductor package 100 that includes a single semiconductor die 102 (or chip). A central processing unit (CPU) 104 and a plurality of switches 106 located along and/or around the periphery of the CPU 104 are integrated on the single semiconductor die 102. In the example of FIG. 1A, the plurality of switches are coupled to the CPU 104 via a metal interconnect layer 108. FIG. 1B illustrates another example of a conventional semiconductor package 108 including two separate semiconductor dies—a first semiconductor die including a switch (switch die 110) and a second semiconductor die including a CPU (CPU die 112). The switch die 110 is coupled to the CPU die 112 via a plurality of wirebonds 114. In the example of FIG. 1B, each of the switch die 110 and the CPU die 112 respectively have power and ground planes.
In both the examples of FIGS. 1A-1B, as a result of the switches being located outside of the periphery of the CPU, when power is needed for the interior circuitry within the CPU, traces or electrical connections (not illustrated) typically have to be run from the periphery of the CPU to the interior of the CPU. Power is often lost or wasted along such traces or electrical connections, thus preventing a CPU from utilizing power efficiently which, in turn, affects an overall performance of the CPU.